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preliminary product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. 1 copyright ? cirrus logic, inc. 1999 (all rights reserved) cirrus logic, inc. p.o. box 17847, austin, texas 78760 (512) 445 7222 fax: (512) 445 7581 http://www.crystal.com cs4954 cs4955 ntsc/pal digital video encoder features l six dacs providing simultaneous composite, s-video, and rgb or component yuv outputs l programmable dac output currents for low imped-ance (37.5 w ) and high impedance (150 w ) loads. l multi-standard support for ntsc-m, ntsc- japan, pal (b, d, g, h, i, m, n, combination n) l itu r.bt656 input mode supporting eav/sav codes and ccir601 master/slave input modes l programmable hsync and vsync timing l multistandard teletext (europe, nabts, wst) support l vbi encoding support l wide-screen signaling (wss) support, eia-j cpx1204 l ntsc closed caption encoder with interrupt l cs4955 supports macrovision copy protection version 7 l host interface configurable for parallel or i 2 c compatible operation l on-chip voltage reference generator l +3.3 v or +5 v operation, cmos, low-power modes, tri-state dacs description the cs4954/5 provides full conversion from digital video formats ycbcr or yuv into ntsc and pal composite, y/c (s-video) and rgb, or yuv analog video. input for- mats can be 27 mhz 8-bit yuv, 8-bit ycbcr, or itu r.bt656 with support for eav/sav codes. video output can be formatted to be compatible with ntsc-m, ntsc- j, pal-b,d,g,h,i,m,n, and combination n systems. closed caption is supported in ntsc. teletext is sup- ported for ntsc and pal. six 10-bit dacs provide two channels for an s-video output port, one or two composite video outputs, and three rgb or yuv outputs. two-times oversampling re- duces the output filter requirements and guarantees no dac-related modulation components within the speci- fied bandwidth of any of the supported video standards. parallel or high-speed i 2 c compatible control interfaces are provided for flexibility in system design. the parallel interface doubles as a general purpose i/o port when the cs4954/5 is in i 2 c mode to help conserve valuable board area. ordering information cs4954-cq 48-pin tqfp CS4955-CQ 48-pin tqfp apr 99 ds278pp4 clk iset dgnd scl sda pdat[7:0] rd wr addr xtal_out vd[7:0] hsync vsync field int reset i 2 c interface host parallel interface color sub-carrier synthesizer 8 video formatter control registers chroma modulate chroma amplifier output interpolate lpf burst insert chroma interpolate lpf luma interpolate luma amplifier sync insert u,v y video timing generator test current reference voltage reference vref r dac y dac cvbs dac c 10-bit dac s vaa xtal_in teletext encoder ttxrq ttxdat ycbcr to rbg b dac g dac 10-bit 10-bit 10-bit 10-bit 10-bit rgb rgb y y 8 color space converter
cs4954 cs4955 2 ds278pp4 table of contents 1. characteristics and specifications ..................................................................5 ac & dc parametric specifications ......................................................................5 recommended operating conditions ..................................................................... 5 dc characteristics ....................................................................................................5 ac characteristic .......................................................................................................7 timing characteristics .............................................................................................8 2. additional cs4954/5 features ...............................................................................10 3. cs4954 introduction .................................................................................................10 4. functional description .........................................................................................10 4.1. video timing generator .........................................................................................10 4.2. video input formatter .............................................................................................11 4.3. color subcarrier synthesizer ..................................................................................11 4.4. chroma path ..........................................................................................................11 4.5. luma path ..............................................................................................................12 4.6. rgb path and component yuv path ....................................................................12 4.7. digital to analog converters ...................................................................................12 4.8. voltage reference ..................................................................................................13 4.9. current reference ..................................................................................................13 4.10. host interface .........................................................................................................13 4.11. closed caption services ........................................................................................13 4.12. teletext services ....................................................................................................14 4.13. wide-screen signaling support and cgms ...........................................................14 4.14. vbi encoding ..........................................................................................................14 4.15. control registers ....................................................................................................14 4.16. testability .............................................................................................................. .14 5. operational description .......................................................................................14 5.1. reset hierarchy ......................................................................................................14 5.2. video timing ...........................................................................................................15 5.2.1. slave mode input interface ..........................................................................15 5.2.2. master mode input interface ........................................................................15 5.2.3. vertical timing .............................................................................................16 5.2.4. horizontal timing .........................................................................................16 5.2.5. ntsc interlaced ..........................................................................................16 5.2.6. pal interlaced .............................................................................................16 5.2.7. progressive scan .........................................................................................17 5.2.8. ntsc progressive scan ..............................................................................17 5.2.9. pal progressive scan .................................................................................18 5.3. itu-r.bt656 ..........................................................................................................18 5.4. digital video input modes .......................................................................................21 5.5. multi-standard output format modes .....................................................................21 5.6. subcarrier generation ............................................................................................21 5.7. subcarrier compensation .......................................................................................21 5.8. closed caption insertion ........................................................................................22 5.9. programmable h-sync and v-sync .........................................................................22 5.10. wide screen signaling (wss) and cgms .............................................................23 contacting cirrus logic support for a complete listing of direct sales, distributor, and sales representative contacts, visit the cirrus logic web site at: http://www.cirrus.com/corporate/contacts/ preliminary product information describes products which are in production, but for which full characterization data is not yet available. advance product infor- mation describes products which are in development and subject to development changes. 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cs4954 cs4955 ds278pp4 3 5.11. teletext support ..................................................................................................... 23 5.12. color bar generator ............................................................................................... 25 5.13. vbi encoding .......................................................................................................... 25 5.14. super white/super black support .......................................................................... 26 5.15. interrupts ............................................................................................................... .26 5.16. general purpose i/o port ....................................................................................... 26 6. filter responses ...................................................................................................... 27 7. analog ...................................................................................................................... .... 30 7.1. analog timing ........................................................................................................ 30 7.2. vref ...................................................................................................................... 30 7.3. iset ...................................................................................................................... .30 7.4. dacs ...................................................................................................................... 30 7.4.1. luminance dac .......................................................................................... 30 7.4.2. chrominance dac ...................................................................................... 30 7.4.3. cvbs dac .................................................................................................. 31 7.4.4. red dac ..................................................................................................... 31 7.4.5. green dac .................................................................................................. 31 7.4.6. blue dac ..................................................................................................... 31 8. programming .............................................................................................................. 32 8.1. host control interface ............................................................................................ 32 8.1.1. i 2 c interface ................................................................................................ 32 8.1.2. 8-bit parallel interface ................................................................................. 33 8.2. register description ............................................................................................... 34 8.2.1. control registers ......................................................................................... 34 9. board design and layout considerations .................................................... 50 9.1. power and ground planes ..................................................................................... 50 9.2. power supply decoupling ...................................................................................... 50 9.3. digital interconnect ................................................................................................ 50 9.4. analog interconnect ............................................................................................... 50 9.5. analog output protection ....................................................................................... 51 9.6. esd protection ....................................................................................................... 51 9.7. external dac output filter ..................................................................................... 51 10. pin description ......................................................................................................... 53 11. package drawing ...................................................................................................... 55
cs4954 cs4955 4 ds278pp4 table of figures 1. video pixel data and control port timing .........................................................................7 2. i 2 c host port timing ..........................................................................................................8 3. reset timing ................................................................................................................ ......9 4. itu r.bt601 input slave mode horizontal timing ..........................................................15 5. itu r.bt601 input master mode horizontal timing ........................................................15 6. vertical timing ............................................................................................................. ....17 7. ntsc video interlaced timing ........................................................................................18 8. pal video interlaced timing ...........................................................................................19 9. ntsc video non-interlaced progressive scan timing ...................................................20 10. pal video non-interlaced progressive scan timing ......................................................20 11. ccir656 input mode timing ...........................................................................................21 12. teletext timing (pulsation mode) ....................................................................................24 13. teletext timing (window mode) ......................................................................................24 14. 1.3 mhz chrominance low-pass filter transfer characteristic ...........................................27 15. 1.3 mhz chrominance low-pass filter transfer characterstic (passband) .........................27 16. 650 khz chrominance low-pass filter transfer characteristic ...........................................27 17. 650 khz chrominance low-pass filter transfer characteristic (passband) ........................27 18. chrominance output interpolation filter transfer characteristic (passband) ......................28 19. luminance interpolation filter transfer characteristic .......................................................28 20. luminance interpolation filter transfer characterstic (passband) .....................................28 21. chrominance interpolation filter transfer characteristic for rgb datapath .......................28 22. chroma interpolator for rgb datapath when rgb_bw=1 (reduced bandwidth) .............29 23. chroma interpolator for rgb datapath when rgb_bw=1 (reduced bandwidth) .............29 24. chroma interpolator for rgb datapath when rgb_bw=0 -3 db .......................................29 25. chroma interpolator for rgb datapath when rgb_bw=0 (full scale) ..............................29 26. i 2 c protocol .................................................................................................................... .32 27. 8-bit parallel host port timing: read-write/write-read cycle ........................................33 28. 8-bit parallel host port timing: address read cycle ......................................................33 29. 8-bit parallel host port timing: address write cycle .......................................................34 30. external low pass filter c 2 should be chosen so that c 1 = c 2 + c cable .........................51 31. typical connection diagram ............................................................................................52
cs4954 cs4955 ds278pp4 5 1. characteristics and specifications absolute maximum ratings ac & dc parametric specifications (agnd,dgnd = 0 v, all voltages with respect to 0 v ) warning: operating beyond these limits can result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd,dgnd = 0 v, all voltages with respect to 0 v.) note: operation outside the ranges is not recommended. dc characteristics (t a = 25 c; vaa, vdd = 5 v; gnda, gndd = 0 v.) parameter symbol min max units power supply vaa/vdd -0.3 6.0 v input current per pin (except supply pins) -10 10 ma output current per pin (except supply pins) -50 +50 ma analog input voltage -0.3 vaa + 0.3 v digital input voltage -0.3 vdd + 0.3 v ambient temperature power applied -55 + 125 c storage temperature -65 + 150 c parameter symbol min typ max units power supplies: digital analog vaa/vdd 3.15 4.75 3.3 5.0 3.45 5.25 v operating ambient temperature ta 0 + 25 + 70 c parameter symbol min typ max units digital inputs high level input voltage v [7:0], pdat [7:0], hsync/vsync/field/clkin vih 2.2 - vdd+0.3 v high level input voltage i 2 c vih 0.7 vdd - - v low level input voltage all inputs - -0.3 - 0.8 v input leakage current - -10 - +10 m a digital outputs high level output voltage lo = -4 ma voh 2.4 - vdd v low level output voltage lo = 4 ma vol - - 0.4 v low level output voltage sda pin only, lo = 6ma vol - - 0.4 v output leakage current high -z digital outputs - -10 - + 10 m a
cs4954 cs4955 6 ds278pp4 dc characteristics (continued) notes: 1. values are by characterization only 2. output current levels with iset = 4 k w , vref = 1.232 v. 3. dacs are set to low impedance mode 4. dacs are set to high impedance mode 5. times for black-to-white-level and white-to-black-level transitions. 6. low-z - 3 dacs on 7. high-z - 6 dacs on parameter symbol min typ max units analog outputs full scale output current cvbs/y/c/r/g/b (notes 1, 2, 3) io 32.9 34.7 36.5 ma full scale output current cvbs/y/c/r/g/b (notes 1, 2, 4) io 8.22 8.68 9.13 ma lsb current cvbs/y/c/r/g/b (notes 1, 2, 3) ib 32.2 33.9 35.7 m a lsb current cvbs/y/c/r/g/b (notes 1, 2, 4) ib 8.04 8.48 8.92 m a dac-to dac matching (note 1) mat - 2 - % output compliance (note 1) voc 0 - + 1.4 v output impedance (note 1) rout - 15 - k w output capacitance (note 1) cout - - 30 pf dac output delay (note 1) odel - 4 12 ns dac rise/fall time (note 1, 5) trf - 2.5 5 ns voltage reference reference voltage output vov 1.170 1.232 1.294 v reference input current (note 1) uvc - - 10 ua power supply supply voltage vaa, vdd 3.15 4.75 3.3 5.0 3.45 5.25 v digital supply current iaa1 - 70 - ma analog supply low-z (note 6) iaa2 - 100 - ma analog supply high-z (note 7) iaa3 - 60 - ma power supply rejection ratio psrr 0.02 0.05 %/% static performance dac resolution (note 1) - - 10 bits differential non-linearity (note 1) dnl -1 + 0.5 + 1 lsb integral non-linearity (note 1) inl - 2 + 1+ 2lsb dynamic performance differential gain (note 1) dg - 2 5 % differential phase (note 1) dp - + 0. 5 + 2 hue accuracy (note 1) ha - - 2 signal to noise ratio snr 70 - - db saturation accuracy (note 1) sat - 1 2 %
cs4954 cs4955 ds278pp4 7 ac characteristic parameter symbol min typ max units pixel input and control port (figure 1) clock pulse high time tch 14.82 18.52 22.58 ns clock pulse low time tcl 14.82 18.52 22.58 ns clock to data set-up time tisu 6 - - ns clock to data hold time tih 0 - - ns clock to data output delay toa - - 17 ns clk v[7:0] (inputs) hsync /vsync cb/field/int (outputs) t ch t cl t isu t ih t oa figure 1. video pixel data and control port timing hsync /vsync
cs4954 cs4955 8 ds278pp4 timing characteristics parameter symbol min typ max units i 2 c host port timing (figure 2) scl frequency fclk 100 1000 khz clock pulse high time tsph 0.1 m s clock pulse low time tspl 0.7 m s hold time (start cond.) tsh 100 ns setup time (start cond.) tssu 100 ns data setup time tsds 50 n s rise time tsr 1 m s fall time tsf 0.3 m s setup time (stop cond.) tss 100 ns bus free time tbuf 100 ns data hold time tdh 0 ns scl low to data out valid tvdo 600 ns sda scl t bu t sh t dh t ds t sh t ss t ssu t si t spi t sr t sph t vdo figure 2. i 2 c host port timing
cs4954 cs4955 ds278pp4 9 timing characteristics (continued) parallel host port timing (figure 27, 28, 29) read cycle time trd 60 - - ns read pulse width trpw 30 - - ns address setup time tas 3 - - ns read address hold time trah 10 - - ns read data access time trda - - 40 ns read data hold time trdh 10 - 50 ns write recovery time twr 60 - - ns write pulse width twpw 40 - - ns write data setup time twds 8 - - ns write data hold time twdh 3 - - ns write-read/read-write recovery time trec 50 - - ns address from write hold time twac 0 - - ns reset timing (figure 3) reset pulse width tres 100 ns reset* t res figure 3. reset timing
cs4954 cs4955 10 ds278pp4 2. additional cs4954/5 features ? five programmable dac output combinations, including yuv and second composite ? optional progressive scan @ mpeg2 field rates ? stable color subcarrier for mpeg2 systems ? general purpose input and output pins ? individual dac power-down capability ? on-chip color bar generator ? supports rs170a and itu r.bt601 compos- ite output timing ? hsync and vsync output in itu r.bt656 mode ? teletext encoding selectable on two composite and s-video signals ? programmable saturation, sch phase, hue, brightness and contrast ? device power-down capability ? super white and super black support 3. cs4954 introduction the cs4954/5 is a complete multi-standard digital video encoder implemented in current cmos tech- nology. the device can operate at 5 v as well as at 3.3 v. itu r.bt601- or itu r.bt656-compliant digital video input is converted into ntsc-m, ntsc-j, pal-b, pal-d, pal-g, pal-h, pal-i, pal-m, pal-n, or pal-n argentina-compatible analog video. the cs4954/5 is designed to con- nect, without glue logic, to mpeg1 and mpeg2 digital video decoders. two 10-bit dac outputs provide high quality s- video analog output while another 10-bit dac si- multaneously generates composite analog video. in addition, there are three more dacs to provide si- multaneous analog rgb or analog yuv outputs. the cs4954/5 will accept 8-bit ycbcr or 8-bit yuv input data. the cs4954/5 is completely configured and con- trolled via an 8-bit host interface port or an i 2 c compatible serial interface. this host port provides access and control of all cs4954/5 options and fea- tures, such as closed caption insertion, interrupts, etc. in order to lower overall system costs, the cs4954/5 provides an internal voltage reference that eliminates the requirement for an external, dis- crete, three-pin voltage reference. in iso mpeg-2 system configurations, the cs4954/5 can be augmented with a common color- burst crystal to provide a stable color subcarrier given an unstable 27 mhz clock input. the use of the crystal is optional, but the facility to connect one is provided for mpeg-2 environments in which the system clock frequency variability is too wide for accurate color sub-carrier generation. 4. functional description in the following subsections, the functions of the cs4954/5 will be described. the descriptions refer to the device elements shown in the block diagram on the cover page. 4.1. video timing generator all timing generation is accomplished via a 27 mhz input applied to the clk pin. the cs4954/5 can also accept a signal from an optional color burst crystal on the xtal_in & xtal_out pins. see the section, color subcarri- er synthesizer, for further details. the video timing generator is responsible for or- chestrating most of the other modules in the device. it operates in harmony with external sync input timing, or it can provide external sync timing out- puts. it automatically disables color burst on appro- priate scan lines and automatically generates serration and equalization pulses on appropriate scan lines.
cs4954 cs4955 ds278pp4 11 the cs4954/5 is designed to function as a video timing master or video timing slave. in both master and slave modes, all timing is sampled and assert- ed with the rising edge of the clk pin. in most cases, the cs4954/5 will serve as the video timing master. hsync , vsync , and field are configured as outputs in master mode. hsync or field can also be defined as a composite blanking output signal in master mode. in master mode, the timing of hsync , vsync , field and compos- ite blank (cb) signals is programmable. exact hor- izontal and vertical display timing is addressed in the operational description section. in slave mode, hsync and vsync are typically configured as input pins and are used to initialize independent vertical and horizontal timing genera- tors upon their respective falling edges. hsync and vsync timing must conform to the itu- r bt.601 specifications. the cs4954/5 also provides a itu r.bt656 slave mode in which the video input stream contains eav and sav codes. in this case, proper hsync and vsync timing are extracted automatically without any inputs other than the v [7:0]. itu r.bt656 input data is sampled with the leading edge of clk. in addition, it is also possible to output hsync and vsync signals during ccir-656 slave mode. 4.2. video input formatter the video input formatter translates ycbcr input data into yuv information, when necessary, and splits the luma and chroma information for filter- ing, scaling, and modulation. 4.3. color subcarrier synthesizer the subcarrier synthesizer is a digital frequency synthesizer that produces the appropriate subcarri- er frequency for ntsc or pal. the cs4954/5 generates the color burst frequency based on the clk input (27 mhz). color burst accuracy and stability are limited by the accuracy of the 27 mhz input. if the frequency varies, then the color burst frequency will also vary accordingly. for environments in which the clk input varies or jitters unacceptably, a local crystal frequency refer- ence can be used on the xtal_in and xtal_out pins. in this instance, the input clk is continuously compared with the external crystal ref- erence input and the internal timing of the cs4954/5 is automatically adjusted so that the color burst fre- quency remains within tolerance. controls are provided for phase adjustment of the burst to permit color adjustment and phase com- pensation. chroma hue control is provided by the cs4954/5 via a 10-bit hue control register (hue_lsb and h_msb). burst amplitude control is also made available to the host via the 8-bit burst amplitude register (sc_amp). 4.4. chroma path the video input formatter delivers 4:2:2 yuv outputs into separate chroma and luma data paths. the chroma path will be discussed here. the chroma output of the video input formatter is directed to a chroma low-pass 19-tap fir filter. the filter bandwidth is selected (or the filter can be bypassed) via the control_1 register. the passband of the filter is either 650 khz or 1.3 mhz and the passband ripple is less than or equal to 0.05 db. the stopband for the 1.3 mhz selection begins at 3 mhz with an attenuation of greater than 35 db. the stopband for the 650 khz selection be- gins around 1.1 mhz with an attenuation of greater than 20 db. the output of the chroma low-pass filter is connect- ed to the chroma interpolation filter in which up- sampling from 4:2:2 to 4:4:4 is accomplished. following the interpolation filter, the u and v chroma signals pass through two independent vari- able gain amplifiers in which the chroma amplitude
cs4954 cs4955 12 ds278pp4 can be varied via the u_amp and v_amp 8-bit host addressable registers. the u and v chroma signals are fed to a quadrature modulator in which they are combined with the output from the subcarrier synthesizer to produce the proper modulated chrominance signal. the chroma then is interpolated by a factor of two in order to operate the output dacs at twice the pixel rate. the interpolated filters enable running the dacs at twice the pixel rate and this helps re- duce the sinx/x roll-off for higher frequencies and reduces the complexity of the external analog low pass filters. 4.5. luma path along with the chroma output path, the cs4954/5 video input formatter initiates a parallel luma data path by directing the luma data to a digital delay line. the delay line is built as a digital fifo in which the depth of the fifo replicates the clock period delay associated with the more complex chroma path. brightness adjustment is also provid- ed via the 8-bit brightness_offset register. following the luma delay, the data is passed through an interpolation filter that has a program- mable bandwidth, followed by a variable gain am- plifier in which the luma dc values are modifiable via the y_amp register. the output of the luma amplifier connects to the sync insertion block. sync insertion is accom- plished by multiplexing, into the luma data path, the different sync dc values at the appropriate times. the digital sync generator takes horizontal sync and vertical sync timing signals and generates the appropriate composite sync timing (including vertical equalization and serration pulses), blank- ing information, and burst flag. the sync edge rates conform to rs-170a or itu r.bt601 and itu r.bt470 specifications. it is also possible to delay the luminance signal, with respect to the chrominance signal, by up to three pixel clocks. this variable delay is useful to offset different propagation delays of the luma baseband and modulated chroma signals. this ad- justable luma delay is available only on the cvbs_1 output. 4.6. rgb path and component yuv path the rgb datapath has the same latency as the luma and chroma path. therefore all six simultaneous analog outputs are synchronized. the 4:2:2 ycbcr data is first interpolated to 4:4:4 and then interpo- lated to 27 mhz. the color space conversion is per- formed at 27 mhz. the coefficients for the color space conversion conform to the itu r.bt601 specifications. after color space conversion, the amplitude of each component can be independently adjusted via the r_amp, g_amp, and b_amp 8-bit host address- able registers. a synchronization signal can be add- ed to either one, two or all of the rgb signals. the synchronization signal conforms to ntsc or pal specifications. some applications (e.g., projection tvs) require analog component yuv signals. the chip provides a programmable mode that outputs component yuv data. sync can be added to the luminance sig- nal. independent gain adjustment of the three com- ponents is provided as well. 4.7. digital to analog converters the cs4954/5 provides six discrete 27 mhz dacs for analog video. the default configuration is one 10-bit dac for s-video chrominance, one 10-bit dac for s-video luminance, one 10-bit dac for composite output, and three 10-bit dacs for rgb outputs. all six dacs are designed for driving ei- ther low-impedance loads (double terminated 75 w ) or high-impedance loads (double terminated 300 w ). there are five different dac configura- tions to choose from (see table 1, below). the dacs can be put into tri-state mode via host- addressable control register bits. each of the six
cs4954 cs4955 ds278pp4 13 dacs has its own associated dac enable bit. in the disable mode, the 10-bit dacs source (or sink) zero current. when running the dacs with a low-impedance load, a minimum of three dacs must be powered down. when running the dacs with a high-imped- ance load, all the dacs can be enabled simulta- neously. for lower power standby scenarios, the cs4954/5 also provides power shut-off control for the dacs. each dac has an associated dac shut-off bit. 4.8. voltage reference the cs4954/5 is equipped with an on-board volt- age reference generator (1.232 v) that is used by the dacs. the internal reference voltage is accu- rate enough to guarantee a maximum of 3% overall gain error on the analog outputs. however, it is possible to override the internal reference voltage by applying an external voltage source to the vref pin. 4.9. current reference the dac output current-per-bit is derived in the current reference block. the current step is speci- fied by the size of resistor placed between the iset current reference pin and electrical ground. a 4 k w resistor needs to be connected between iset pin and gnda. the dac output currents are optimized to either drive a doubly terminated load of 75 w (low impedence mode) or a double termi- nated load of 300 w (high impedence mode). the 2 output current modes are software selectable through a register bit. 4.10. host interface the cs4954/5 provides a parallel 8-bit data inter- face for overall configuration and control. the host interface uses active-low read and write strobes, along with an active-low address enable signal, to provide microprocessor-compatible read and write cycles. indirect host addressing to the cs4954/5 in- ternal registers is accomplished via an internal ad- dress register that is uniquely accessible via bus write cycles in which the host address enable signal is asserted. the cs4954/5 also provides an i 2 c-compatible se- rial interface for device configuration and control. this port can operate in standard (100kb/sec) or fast (400 kb/sec) modes. when in i 2 c mode, the parallel data interface pins, pdat [7:0], can be used as a general purpose i/o port controlled by the i 2 c interface. 4.11. closed caption services the cs4954/5 supports the generation of ntsc closed caption services. line 21 and line 284 cap- tioning can be generated and enabled independent- ly via a set of control registers. when enabled, clock run-in, start bit, and data bytes are automati- cally inserted at the appropriate video lines. a con- venient interrupt protocol simplifies the software interface between the host processor and the cs4954/5. dac pin # mode 1 mode 2 mode 3 mode 4 mode 5 y 48 y y y cvbs_2 cvbs_2 c47ccc - - cvbs 44 cvbs_1 cvbs_1 cvbs_1 cvbs_1 cvbs_1 r 39 r cr (v) - r cr (v) g 40 g y cvbs_2 g y b43bcb (u)- bcb (u) table 1. dac configuration modes
cs4954 cs4955 14 ds278pp4 4.12. teletext services the cs4954/5 encodes the most common teletext formats, such as european teletext, world stan- dard teletext (pal and ntsc), and north ameri- can teletext (nabts). teletext data can be inserted in any of the tv lines (blanking lines as well as active lines). in addition the blanking lines can be individually allocated for teletext instantiation. the input timing for teletext data is user program- mable. see the section teletext services for further details. teletext data can be independently inserted on ei- ther one or all of the cvbs_1, cvbs_2, or s-video signals. 4.13. wide-screen signaling support and cgms insertion of wide-screen signal encoding for pal and ntsc standards is supported and cgms (copy generation management system) for ntsc in japan. wide-screen signals are inserted in lines 23 and 336 for pal, and lines 20 and 283 for ntsc. 4.14. vbi encoding this chip supports the transmission of control sig- nals in the vertical blanking time interval according to smpte rp 188 recommendations. vbi encoded data can be independently inserted into either or all of cvbs_1, cvbs_2 or s-video signals. 4.15. control registers the control and configuration of the cs4954/5 is accomplished primarily through the control regis- ter block. all of the control registers are uniquely addressable via the internal address register. the control register bits are initialized during device reset. see the programming section of this data sheet for the individual register bit allocations, bit operation- al descriptions, and initialization states. 4.16. testability the digital circuits are completely scanned by an internal scan chain, thus providing close to 100% fault coverage. 5. operational description 5.1. reset hierarchy the cs4954/5 is equipped with an active low asyn- chronous reset input pin, reset . reset is used to initialize the internal registers and the internal state machines for subsequent default operation. see the electrical and timing specification section of this data sheet for specific cs4954/5 device reset and power-on signal timing requirements and re- strictions. while the reset pin is held low, the host interface in the cs4954/5 is disabled and will not respond to host-initiated bus cycles. all outputs are valid after a time period following reset pin low. a device reset initializes the cs4954/5 internal registers to their default values as described by ta- ble 9, control registers. in the default state, the cs4954/5 video dacs are disabled and the device is internally configured to provide blue field video data to the dacs (any input data present on the v [7:0] pins is ignored at this time). otherwise, the cs4954/5 registers are configured for ntsc-m itu r.bt601 output operation. at a minimum, the dac registers (0x04 and 0x05) must be written (to enable the dacs) and the in_mode bit of the control_0 register (0x01) must be set (to en- able itu r.bt601 data input on v [7:0]) for the cs4954/5 to become operational after reset.
cs4954 cs4955 ds278pp4 15 5.2. video timing 5.2.1. slave mode input interface in slave mode, the cs4954/5 receives signals on vsync and hsync as inputs. slave mode is the default following reset and is changed to master mode via a control register bit (control_0 [4]). the cs4954/5 is limited to itu r.bt601 horizon- tal and vertical input timing. all clocking in the cs4954/5 is generated from the clk pin. in slave mode, the sync generator uses externally provided horizontal and vertical sync signals to synchronize the internal timing of the cs4954/5. video data that is sent to the cs4954/5 must be synchronized to the horizontal and vertical sync signals. figure 4 illus- trates horizontal timing for itu r.bt601 input in slave mode. note that the cs4954/5 expects to re- ceive the first active pixel data on clock cycle 245 (ntsc) when control_2 register (0x02) bit sync_dly = 0. when sync_dly = 1, it expects the first active pixel data on clock cycle 246 (ntsc). 5.2.2. master mode input interface the cs4954/5 defaults to slave mode following reset high but can be switched into master mode via the mstr bit in the control_0 register (0x00). in master mode, the cs4954/5 uses the vsync , hsync and field device pins as out- puts to schedule the proper external delivery of dig- ital video into the v [7:0] pins. figure 5 illustrates horizontal timing for the ccir601 input in master mode. the timing of the hsync output is selectable in the prog_hs registers (0x0d, 0x0e). hsync can be delayed by one full line cycle. the timing of the vsync output is also selectable in the clk 1706 active pixel #720 hsync (input) v[7:0] (sync_dly=0) 1705 1704 1703 1728 1 23 128 129 264 265 266 267 268 1686 1685 1684 1683 1716 1 23 128 129 244 245 246 247 248 y cr y cb y cr y horizontal blanking active pixel #1 active pixel #2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ntsc 27mhz clock count pal 27mhz clock count 1702 1682 active pixel #720 v[7:0] (sync_dly=1) y cr y cb y cr horizontal blanking active pixel #1 active pixel #2 cb active pixel #719 figure 4. itu r.bt601 input slave mode horizontal timing clk 1706 active pixel #720 hsync (output) v[7:0] 1705 1704 1703 1728 1 23 128 129 264 265 266 267 268 1686 1685 1684 1683 1716 1 23 128 129 244 245 246 247 248 y cr y cb y cr y horizontal blanking active pixel #1 active pixel #2 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ntsc 27mhz clock count pal 27mhz clock count cb (output) 1702 1682 figure 5. itu r.bt601 input master mode horizontal timing
cs4954 cs4955 16 ds278pp4 prog_vs register (0x0d). vsync can be de- layed by thirteen lines or advanced by eighteen lines. 5.2.3. vertical timing the cs4954/5 can be configured to operate in any of four different timing modes: pal, which is 625 vertical lines, 25 frames per second interlaced; ntsc, which is 525 vertical lines, 30 frames per second interlaced; and either pal or ntsc in pro- gressive scan, in which the display is non-inter- laced. these modes are selected in the control_0 register (0x00). the cs4954/5 conforms to standard digital decom- pression dimensions and does not process digital input data for the active analog video half lines as they are typically in the over/underscan region of televisions. 240 active lines total per field are pro- cessed for ntsc, and 288 active lines total per field are processed for pal. frame vertical dimen- sions are 480 lines for ntsc and 576 lines for pal. table 2 specifies active line numbers for both ntsc and pal. refer to figure 6 for hsync , vsync and field signal timing. 5.2.4. horizontal timing hsync is used to synchronize the horizontal-in- put-to-output timing in order to provide proper hor- izontal alignment. hsync defaults to an input pin following reset but switches to an output in mas- ter mode (control_0 [4] = 1). horizontal tim- ing is referenced to hsync transitioning low. for active video lines, digital video input is to be ap- plied to the v [7:0] inputs for 244 (ntsc) or for 264 (pal) clk periods following the leading (falling) edge of hsync if the prog_hs regis- ters are set to default values. 5.2.5. ntsc interlaced the cs4954/5 supports ntsc-m, ntsc-j and pal-m modes where there are 525 total lines per frame and two fixed 262.5-line fields per frame and 30 total frames occurring per second. ntsc inter- laced vertical timing is illustrated in figure 7. each field consists of one line for closed caption, 240 ac- tive lines of video, plus 21.5 lines of blanking. vsync field one transitions low at the beginning of line four and will remain low for three lines or 2574 pixel cycles (858 3). the cs4954/5 exclu- sively reserves line 21 of field one for closed cap- tion insertion. digital video input is expected to be delivered to the cs4954/5 v [7:0] pins for 240 lines beginning on active video lines 22 and con- tinuing through line 261. vsync field two transi- tions low in the middle of line 266 and stays low for three line-times and transitions high in the middle of line 269. the cs4954/5 exclusively reserves line 284 of field two for closed caption insertion. video input on the v [7:0] pins is expected between lines 285 through line 525. 5.2.6. pal interlaced the cs4954/5 supports pal modes b, d, g, h, i, n, and combination n, in which there are 625 total lines per frame, two fixed 312.5 line fields per frame, and 25 total frames per second. figure 8 il- lustrates pal interlaced vertical timing. each field consists of 287 active lines of video plus 25.5 lines of blanking. vsync will transition low to begin field one and will remain low for 2.5 lines or 2160 pixel cycles (864 2.5). digital video input is expected to be delivered to the cs4954/5 v [7:0] pins for 287 lines beginning on active video line 24 and continu- ing through line 310. field two begins with vsync transitioning low after 312.5 lines from the beginning of field one. mode field active lines ntsc 1, 3; 2, 4 22-261; 285-524 pal 1, 3, 5, 7; 2, 4, 6, 8 23-310; 336-623 ntsc progressive-scan na 22-261 pal progressive-scan na 23-310 table 2. vertical timing
cs4954 cs4955 ds278pp4 17 vsync stays low for 2.5 line-times and transitions high with the beginning of line 315. video input on the v [7:0] pins is expected between line 336 through line 622. 5.2.7. progressive scan the cs4954/5 supports a progessive scan mode in which the video output is non-interlaced. this is accomplished by displaying only the odd video field for ntsc or pal. to preserve precise mpeg-2 frame rates of 30 and 25 per second, the cs4954/5 displays the same odd field repetitively but alternately varies the field times. this mode is in contrast to other digital video encoders, which commonly support progressive scan by repetitively displaying a 262 line field (524/525 lines for ntsc). the common method is flawed: over time, the output display rate will overrun a system-clock- locked mpeg-2 decompressor and display a field twice every 8.75 seconds. 5.2.8. ntsc progressive scan vsync will transition low at line four to begin field one and will remain low for three lines or 2574 pixel cycles (858 3). ntsc interlaced tim- ing is illustrated in figure 9. in this mode, the cs4954/5 expects digital video input at the v [7:0] ntsc vertical timing (odd field) line hsync vsync field 3 4 5 6 7 8 9 10 ntsc vertical timing (even field) pal vertical timing (odd field) pal vertical timing (even field) 264 265 266 267 268 269 270 271 265 1 2 3 4 5 6 7 311 312 313 314 315 316 317 318 line hsync vsync field line hsync vsync field line hsync vsync field figure 6. vertical timing
cs4954 cs4955 18 ds278pp4 pins for 240 lines beginning on active video line 22 and continuing through line 261. field two begins with vsync transitioning low at line 266. vsync stays low for 3 line cycles and transitions high during the end of line 268. video input on the v [7:0] pins is expected between line 284 and line 522. field two is 263 lines; field one is 262 lines. 5.2.9. pal progressive scan vsync will transition low at the beginning of the odd field and will remain low for 2.5 lines or 2160 pixel cycles (864 2.5). pal non-interlaced tim- ing is illustrated in figure 10. in this mode, the cs4954/5 expects digital video input on the v [7:0] pins for 288 lines, beginning on active video line 23 and continuing through line 309. the second begins with vsync transitioning low after 312 lines from the beginning of the first field. vsync stays low for 2.5 line-times and transitions high during the middle of line 315. video input on the v [7:0] pins is expected between line 335 through line 622. field two is 313 lines; field one is 312 lines. 5.3. itu-r.bt656 the cs4954/5 supports an additional itu- r.bt656 slave mode feature that is selectable through the itu-r.bt656 bit of the control_0 register. the itu-r.bt656 slave feature is unique because the horizontal and vertical timing and dig- ital video are combined into a single 8-bit 27 mhz input. with itu-r.bt656 there are no horizontal and vertical input or output strobes, only 8-bit 27 mhz active cbycry data, with start- and end- of-video codes implemented using reserved 00 and ff code sequences within the video feed. as with all modes, v [7:0] are sampled with the rising edge of clk. the cs4954/5 expects the digital itu- r.bt656 stream to be error-free. the field out- 523 524 525 1 2 3 4 5 6 7 8 9 vsync drops 10 22 analog field 1 261 262 263 analog field 2 285 284 272 271 270 269 268 267 266 265 264 523 524 525 1 23456 789 vsync drops 10 22 analog field 3 261 262 263 analog field 4 285 284 272 271 270 269 268 267 266 265 264 burst begins with positive half-cycle burst begins with negative half-cycle figure 7. ntsc video interlaced timing
cs4954 cs4955 ds278pp4 19 put toggles as with non itu-r.bt656 input. itu- r.bt656 input timing is illustrated in figure 11. as mentioned above, there are no horizontal and vertical timing signals necessary in itu-r.bt656 mode. however in some cases it is advantageous to output these timing signals for other purposes. by setting the 656_sync_out register bit in control_6 register, hsync and vsync are output,so that other devices in the system can syn- chronize to these timing signals. 621 622 623 analog field 1 burst phase = 135 degrees relative to u burst phase = 225 degrees relative to u 620 624 625 1 2 3 4 5 6 7 23 24 309 310 analog field 2 308 311 312 313 314 315 316 317 318 319 320 336 337 621 622 623 analog field 3 620 624 625 1 2 3 4 5 6 7 23 24 309 310 analog field 4 308 311 312 313 314 315 316 317 318 319 320 336 337 621 622 623 analog field 5 620 624 625 1 2 3 4 5 6 7 23 24 309 310 analog field 6 308 311 312 313 314 315 316 317 318 319 320 336 337 621 622 623 analog field 7 620 624 625 1 2 3 4 5 6 7 23 24 309 310 analog field 8 308 311 312 313 314 315 316 317 318 319 320 336 337 vsync drops figure 8. pal video interlaced timing
cs4954 cs4955 20 ds278pp4 261 262 123456789 start of vsync 10 22 field 1 burst begins with positive half-cycle burst begins with negative half-cycle burst phase = reference phase = 180 relative to b-y 0 burst phase = reference phase = 180 relative to b-y 0 262 263 12345678910 22 261 262 12345678910 22 262 263 12345678910 22 field 2 field 3 field 4 start of vsync figure 9. ntsc video non-interlaced progressive scan timing 309 310 311 analog field 1 burst phase = 135 degrees relative to u burst phase = 225 degrees relative to u 312 313 1 2 3 4 5 6 7 23 24 309 analog field 2 308 311 312 vsync drops 12345 6 7 23 24 310 309 310 311 analog field 3 312 313 1 2 3 4 5 6 7 23 24 309 analog field 4 308 311 312 12345 6 7 23 24 310 figure 10. pal video non-interlaced progressive scan timing
cs4954 cs4955 ds278pp4 21 5.4. digital video input modes the cs4954/5 provides two different digital video input modes that are selectable through the in_mode bit in the control_0 register. in mode 0 and upon reset, the cs4954/5 de- faults to output a solid color (one of a possible of 256 colors). the background color is selected by writing the bkg_color register (0x08). the colorspace of the register is rgb 3:3:2 and is unaf- fected by gamma correction. the default color fol- lowing reset is blue. in mode 1 the cs4954/5 supports a single 8-bit 27 mhz cbycry source as input on the v [7:0] pins. input video timing can be itu-r.bt601 mas- ter or slave and itu-r.bt656. 5.5. multi-standard output format modes the cs4954/5 supports a wide range of output for- mats compatible with worldwide broadcast stan- dards. these formats include ntsc-m, ntsc-j, pal-b/d/g/h/i, pal-m, pal-n, and pal com- bination n (pal-nc) which is the broadcast stan- dard used in argentina. after reset, the cs4954/5 defaults to ntsc-m operation with itu r.bt 601 analog timing. ntsc-j can also be supported in the japanese format by turning off the 7.5 ire pedestal through the ped bit in the control_1 register (0x01). output formats are configured by writing control registers with the values shown in table 3. 5.6. subcarrier generation the cs4954/5 automatically synthesizes ntsc and pal color subcarrier clocks using the clk fre- quency and four control registers (sc_synth0/1/2/3). the ntsc subcarrier syn- thesizer is reset every four fields (every eight fields for pal). the sc_synth0/1/2/3 registers used together provide a 32-bit value that defaults to ntsc (43e0f83eh) following reset. table 4 shows the 32-bit value required for each of the different broadcast formats. 5.7. subcarrier compensation since the subcarrier is synthesized from clk the subcarrier frequency error will track the clock fre- quency error. if the input clock has a tolerance of 200 ppm then the resulting subcarrier will also have a tolerance of 200 ppm. per the ntsc speci- fication, the final subcarrier tolerance is 10 hz y cr y ff 00 00 xy 80 10 80 10 80 10 80 10 80 10 80 10 80 10 ff 00 00 xy cb y cr cb y cr 1440 clocks active video sav code composite video ancilliary data 268 clocks (ntsc) 280 clocks (pal) horizontal blanking eav code 4 clocks active video v[7:0] itu r.bt656 4 clocks figure 11. ccir656 input mode timing data system fsubcarrier value (hex) ntsc-m, ntsc-j 3.5795455 mhz 43e0f83e pal-b, d, g, h, i, n 4.43361875 mhz 54131596 pal-n (argentina) 3.582056 mhz 43ed288d pal-m 3.579611 mhz 43cddfc7 table 3.
cs4954 cs4955 22 ds278pp4 which is approximately 3 ppm. care must be taken in selecting a suitable clock source. in mpeg-2 system environments the clock is actu- ally recovered from the data stream. in these cases the recovered clock can be 27 mhz 50 ppm or 1350 hz. it varies per television, but in many cas- es given an mpeg-2 system clock of 27 mhz, 1350 hz, the resultant color subcarrier produced will be outside of the televisions ability to com- pensate and the chrominance information will not be displayed (resulting in a black-and-white picture only). the cs4954/5 is designed to provide automatic compensation for an excessively inaccurate mpeg-2 system clock. sub-carrier compensation is enabled through the xtal bit of the control_2 register. when enabled the cs4954/5 will utilize a common quartz color burst crystal (3.579545 mhz 50 ppm for ntsc) at- tached to the xtal_in and xtal_out pins to automatically compare and compensate the color subcarrier synthesis process. 5.8. closed caption insertion the cs4954/5 is capable of ntsc closed caption insertion on lines 21 and 284 independently. closed captioning is enabled for either one or both lines via the cc_en [1:0] register bits and the data to be inserted is also written into the four closed caption data registers. the cs4954/5, when enabled, automatically generates the seven cycles of clock run-in (32 times the line rate), start bit insertion (001), and finally insertion of the two data bytes per line. data low at the video outputs corresponds to 0 ire and data high corresponds to 50 ire. there are two independent 8-bit registers per line (cc_21_1 & cc_21_2 for line 21 and cc_284_1 & cc_284_2 for line 284). interrupts are also pro- vided to simplify the handshake between the driver software and the device. typically the host would write all 4 bytes to be inserted into the registers and then enable closed caption insertion and interrupts. as the closed caption interrupts occur the host soft- ware would respond by writing the next two bytes to be inserted to the correct control registers and then clear the interrupt and wait for the next field. 5.9. programmable h-sync and v-sync it is possible in master mode to change the h-sync and v-sync times based on register settings. pro- grammable h-sync and v-sync timings are helpful in several digital video systems, where latencies of the control signals are present. the user can then program h-sync and v-sync timing according to their system requirements. the default values are 244, and 264 for ntsc and pal respectively. address register ntsc-m itu r.bt601 ntsc-j itu r.bt601 ntsc-m rs170a pal- b,d,g,h,i pal-m pal-n pal-n comb. (argent) 000 control_0 01h 01h 21h 41h 61h a1h 81h 001 control_1 12h 10h 16h 30h 12h 30h 30h 004 control_4 07h 07h 07h 07h 07h 07h 07h 005 control_5 78h 78h 78h 78h 78h 78h 78h 010 sc_amp 1ch 1ch 1ch 15h 15h 15h 15h 011 sc_synth0 3eh 3eh 3eh 96h c7h 96h 8ch 012 sc_synth1 f8h f8h f8h 15h dfh 15h 28h 013 sc_synth2 e0h e0h e0h 13h cdh 13h edh 014 sc_synth3 43h 43h 43h 54h 43h 54h 43h table 4. multi-standard format register configurations
cs4954 cs4955 ds278pp4 23 h-sync can be delayed by a full line, in 74 nsec in- tervals. v-sync can be shifted in both directions in time. the default values are 18 and 23 for ntsc and pal respectively. since the v-sync register is 5 bits wide (sync register 0), the v-sync pulse can be shifted by 31 lines in total. v-sync can preceed by a maximum of 18 lines (ntsc) or 23 lines (pal) respectively from its de- fault location, and v-sync can follow by a maxi- mum of 13 lines (ntsc) or 8 lines (pal) from its default location. 5.10. wide screen signaling (wss) and cgms wide screen signaling support is provided for ntsc and for pal standards. wide screen signal- ing is currently used in most countries with 625 line systems as well as in japan for edtv-ii applica- tions. for complete description of wss standard, please refer to itu-r bt.1119 (625 line system) and to eiaj cpx1204 for the japanese 525 line system. the wide screen signal is transferred in a blanking line of each video field (ntsc: lines 20 and 283, pal: lines 23 and 336). wide screen signaling is enabled by setting ww_23 to 1. some countries with pal standard dont use line 336 for wide screen signaling (they use only line 23), therefore we provide another enable bit (wss_22) for that particular line. there are 3 registers dedicated to contain the trans- mitted wss bits (wss_reg_0, wss_reg_1, wss_reg_2). the data insertion into the appro- priate lines are performed automatically by this de- vice. the run-in and start code bits do not have to be loaded into this device, it automatically inserts the correct code at the beginning of transfer. 5.11. teletext support this chip supports several teletext standards, like european teletext, nabts (north american tele- text), and wst (world standard teletext) for ntsc and pal. all these teletext standards are defined in the itu- r bt.653-2 document. the european teletext is defined as teletext system b for 625/50 hz tv systems. nabts teletext is defined as teletext system c for 525/60 hz tv systems. wst for pal is defined as teletext system d for 624/50 hz tv systems and wst for ntsc is de- fined as teletext system d for 525/60 hz tv systems. this chip provides independant teletext encoding into composite 1, composite 2 and s-video signals. the teletext encoding into these various signals is software programmable. in teletext pulsation mode, (ttx_window=0), register 031 bit 3, the pin ttxdat receives a teletext bitstream sampled at the 27 mhz clock. at each rising edge of the ttxrq output signal a sin- gle teletext bit has to be provided after a program- mable input delay at the ttxdat input pin. phase variant interpolation is achieved on this bit- stream in the internal teletext encoder, providing sufficient small phase jitter on the ouput text lines. ttxrq provides a fully programmable request signal to the teletext source, indicating the insertion period of the bitstream at indepenantly selectable lines for both tv fields. the internal insertion win- dow for text is set to either 360, 296 or 288 teletext bits, depending on the selected teletext standard. the clock run-in is included in this window. teletext in enabled by setting the ttx_en bit to 1. the ttx_wst bit in conjunction with the tv_format register select one of the 4 possible teletext encoding possibilities. the teletext timing is shown in the figure 12. ttxhs and ttxhd are user programmable and
cs4954 cs4955 24 ds278pp4 therefore allow the user to have full control over to when sending teletext data to this device. the time t fd is the time needed to interpolate tele- text input data and inserting it into the cvbs and y output signals, such that it appears between t ttx = 9.8 m s and t ttx =12 m s after the leading edge of the horizontal synchronization pulse. t fd changes with the tv standard and the selected teletext standard. please refer to itu-r bt.653-2 for more detailed information. the time t pd is the pipeline delay time introduced by the source that is gated by ttxrq in order to deliver teletext data. this delay is programmable through the register ttxhd. for every active high transition at output pin ttxrq, a new tele- text bit must be provided by the source. the time between the beginning of the first ttxrq pulse and the leading edge of h-sync is programmable through the ttxhs register. since the beginning of the pulses representing the ttxrq signal and the delay between the rising edge of ttxrq and valid teletext input data are fully programmable, the ttxdat data is always inserted at the correct position after the leading edge of the outgoing horizontal synchronization pulse. the time t ttxwin is the internally used insertion window for ttx data; it has a constant length depending on the selected teletext standard which allows insertion of 360 ttx bits (6.9375 mbit/sec) (european teletext) or 296 ttx bits (5.6427875 mbit/sec) (wst pal) or 288 ttx bits (5.727272 mbit/sec) (nabts) or 296 ttx bits (5.727272 mbit/sec) (wst ntsc) respectively. using the appropriate programming, all suitable lines of the odd field (ttxovs through ttx- ove) plus all suitable lines of the even field (ttxevs through ttxeve) can be used for tele- text insertion. in addition it is possible to selec- tively disable the teletext insertion on single lines. this can be programmed by setting the ttx_line_dis1, ttx_line_dis2 and ttx_line_dis3 registers appropriately. note that the ttxdat signal must be synchro- nized with the 27 mhz clock. the pulse width of the ttxrq signal varies between three and four 27 mhz clock cycles. the variation is necessary in order to maintain the strict timing requirements of the teletext standard. table 5 shows how to program the ttxhs register for teletext instantiation into the analog signals for the various supported tv formats. ttxhs is the time between the leading edge of the hsync sig- nal and the rising edge of the first ttxrq signal and consists of multiples of 27 mhz clock cycles note that with increasing values of ttxhs the time t ttx increases as well. the time t fd accounts for the internal pipeline delay due to processing, synchronization and instantiation of the teletext data. the time t pd is dependant on the ttxhd register. figure 12. teletext timing (pulsation mode) figure 13. teletext timing (window mode) cvbs/y ttxrq ttxdat textbit #:12345 t ttx t ttxwin t pd t fd cvbs/y ttxrq ttxdat textbit #:12345 t ttx t ttxwin t pd t fd
cs4954 cs4955 ds278pp4 25 note that the teletext databits are shaped according to the itu r.bt653-2 specifications. if register 031 bit 3 is set, (ttx_window=1) the teletext is in windows mode, the request pulses become a window where the bit provided on the ttxdat pin are valid (see figure 13). alternately to the pulsation mode (where the num- ber of request pulses are determined by the teletext standard chosen), the length of the window must be programmed by the user independently of the tele- text standard used. the length of the window is programmed through register 029 ttxhs (start of window) and register 02a (ttxhd) and 031 (end of window). the end-of-window register is a 11 bit value. in teletext window mode, the ttxhs value can be selected using the values in table 5. although these values may need to be adjusted to match your system delay, use the following equation to com- pute the ttxhd value: ttxhs + 1402 = ttxhd (for europe) ttxhs + 1151 = ttxhd (for wst) ttxhs + 1122 = ttxhd (for nabts) 5.12. color bar generator the cs4954/5 is equipped with a color bar genera- tor that is enabled through the cbar bit of the control_1 register. the color bar generator works in master or slave mode and has no effect on the video input/output timing. if the cs4954/5 is configured for slave mode color bars, proper video timing must be present on the hsync and vsync pins for the color bars to be displayed. given proper slave mode input timing or master mode, the color bar generator will override the vid- eo input pixel data. the output of the color bar generator is instantiated after the chroma interpolation filter and before the luma delay line. the generated color bar numbers are for 100% amplitude, 100% saturation ntsc eia color bars or 100% amplitude, 100% satura- tion pal ebu color bars. for pal color bars, the cs4954/5 generates ntsc color bar values, which are very close to standard pal values. the exact luma and chroma values are listed in table 6. . 5.13. vbi encoding vbi (vertical blanking interval) encoding is per- formed according to smpte rp 188 recommenda- tions. in ntsc mode lines 10 - 20 and lines 272 - 283 are used for the transmission of ancillary data. in pal mode lines 6 - 22 and lines 318 -335 are used. the vbi encoding mode can be set through the control_3 register. all digital input data is passed through the chip when this mode is enabled. it is therefore the re- sponsibility of the user to ensure appropriate ampli- tv standard teletext standard ttxhs (register value) t ttx ntsc-m nabts 161 10.5 m s ntsc-m wst-ntsc 142 9.8 m s pal-b europe ttx 204 12.0 m s pal-b wst-pal 163 10.5 m s pal-m nabts 161 10.5 m s pal-m wst-ntsc 142 9.8 m s pal-n (non arg.) europe ttx 204 12.0 m s pal-n (non arg.) wst-pal 163 10.5 m s pal-n (arg.) europe ttx 204 12.0 m s pal-n (arg.) wst-pal 163 10.5 m s table 5. teletext timing parameters color cb cr y white 0 0 + 167 yellow - 84 + 14 + 156 cyan + 28 - 84 + 138 green - 56 - 70 + 127 magenta + 56 + 70 + 110 red - 28 + 84 + 99 blue + 84 - 14 + 81 black 0 0 + 70 table 6. internal color bar values (8-bit values, cb/cr are in twos complement format)
cs4954 cs4955 26 ds278pp4 tude levels. table 7 shows the relationship of the digital input signal and the analog output voltage. each lsb corresponds to a step of 5 mv in the out- put voltage. 5.14. super white/super black support the itu-r bt.601 recommendation limits the al- lowed range for the digital video data between 010 - 0eb for luma and between 010 - 0f0 for the chrominance values. this chip will clip any digital input value which is out of this range to con- form to the itu-r bt.601 specifications. however for some applications it is useful to allow a wider input range. by setting the clip_off bit (control_6 register) the allowed input range is extended between 001 - 0fe for both luma and chrominance values. note that 000 and 0ff values are never allowed, since they are reserved for synchronization infor- mation. 5.15. interrupts in order to better support precise video mode switches and to establish a software/hardware handshake with the closed caption insertion block the cs4954/5 is equipped with an interrupt pin named int. the int pin is active high. there are three interrupt sources: vsync , line 21, and line 284. each interrupt can be individually disabled with the int_en register. each interrupt is also cleared via writing a one to the corresponding int_clr register bits. the three individual inter- rupts are or-ed together to generate an interrupt signal which is presented on the int output pin. if an interrupt has occurred, it cannot be eliminated with a disable, it must be cleared. 5.16. general purpose i/o port the cs4954/5 has a gpio port and register that is available when the device is configured for i 2 c host interface operation. in i 2 c host interface mode, the pdat [7:0] pins are unused by the host interface and they can operate as input or output pins for the gpio_data_reg register (00a). the cs4954/5 also contains the gpio_ctrl_reg register (009) which is used to configure the gpio pins for input or output op- eration. the gpio port pdat [7:0] pins are configured for input operation when the corresponding gpio_ctrl_reg [7:0] bits are set to 0. in gpio input mode, the cs4954/5 will latch the data on the pdat [7:0] pins into the corresponding bit loca- tions of gpio_data_reg when it detects regis- ter address 00a through the i 2 c interface. a detection of address 00a can happen in two ways. the first and most common way this will happen is when address 00a is written to the cs4954/5 via its i 2 c interface. the second method for detecting address 00a is implemented by accessing register address 009 through i 2 c. in i 2 c host interface op- eration, the cs4954/5 register address pointer will auto-increment to address 00a after an address 009 access. the gpio port pdat [7:0] pins are configured for output operation when the corresponding gpio_ctrl_reg [7:0] bits are set. in gpio out- put mode, the cs4954/5 will output the data in gpio_data_reg [7:0] bit locations onto the corresponding pdat [7:0] pins when it detects a register address 00a through the i 2 c interface. digital input analog output voltage 0 38 286 mv 0 3b 300 mv 0 c4 1000 mv table 7. vbi encoding signal amplitudes
cs4954 cs4955 ds278pp4 27 6. filter responses 0 1 2 3 4 5 6 x 10 6 -70 -60 -50 -40 -30 -20 -10 0 1.3 mhz. filter frequency response magnitude - db frequency (hz) figure 14. 1.3 mhz chrominance low-pass filter trans- fer characteristic figure 15. 1.3 mhz chrominance low-pass filter trans- fer characterstic (passband) 0 2 4 6 8 10 12 x 10 5 -0.5 -0.4 -0.3 -0.2 -0.1 0 1.3 mhz. filter passband response magnitude - db frequency (hz) 0 1 2 3 4 5 6 x 10 6 -30 -25 -20 -15 -10 -5 0 650 khz. filter frequency response magnitude - db figure 16. 650 khz chrominance low-pass filter trans- fer characteristic figure 17. 650 khz chrominance low-pass filter trans- fer characteristic (passband) 0 2 4 6 8 10 12 x 10 5 -3 -2.5 -2 -1.5 -1 -0.5 0 650 khz. filter passband response magnitude - db
cs4954 cs4955 28 ds278pp4 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 chroma output interpolator pass band frequency (mhz) magnitude response (db) figure 18. chrominance output interpolation filter transfer characteristic (passband) figure 19. luminance interpolation filter transfer char- acteristic 0 2 4 6 8 10 12 14 -40 -35 -30 -25 -20 -15 -10 -5 0 luma output interpolation filter response at 27mhz full scale frequency (mhz) magnitude response (db) 0 1 2 3 4 5 6 7 8 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 luma output interpolation filter response at 27 mhz (-3 db) frequency (mhz) magnitude response (db) figure 20. luminance interpolation filter transfer char- acterstic (passband) figure 21. chrominance interpolation filter transfer characteristic for rgb datapath 0 2 4 6 8 10 12 -40 -35 -30 -25 -20 -15 -10 -5 0 rgb datapath filter for rgb_bw = 0 full scale frequency (mhz) magnitude response (db)
cs4954 cs4955 ds278pp4 29 0 2 4 6 8 10 12 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 rgb datapath filter when rgb_bw = 1 (reduced bandwidth) (-3 db) frequency (mhz) magnitude response (db) figure 22. chroma interpolator for rgb datapath when rgb_bw=1 (reduced bandwidth) figure 23. chroma interpolator for rgb datapath when rgb_bw=1 (reduced bandwidth) 0 2 4 6 8 10 12 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 rgb datapath filter when rgb_bw = 1 (reduced bandwidth) frequency (mhz) magnitude response (db) 0 2 4 6 8 10 12 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5 1 rgb datapath filter for rgb_bw = 0 (-3 db) frequency (mhz) magnitude response (db) figure 24. chroma interpolator for rgb datapath when rgb_bw=0 -3 db figure 25. chroma interpolator for rgb datapath when rgb_bw=0 (full scale) 0 5 10 15 20 25 -40 -35 -30 -25 -20 -15 -10 -5 0 chroma output interpolator full scale frequency (mhz) magnitude response (db)
cs4954 cs4955 30 ds278pp4 7. analog 7.1. analog timing all cs4954/5 analog timing and sequencing is de- rived from 27 mhz clock input. the analog outputs are controlled internally by the video timing genera- tor in conjunction with master and slave timing. the video output signals perform accordingly for ntsc and pal specifications. being that the cs4954/5 is almost entirely a digital circuit, great care has been taken to guarantee ana- log timing and slew rate performance as specified in the ntsc and pal analog specifications. refer- ence the analog parameters section of this data sheet for exact performance parameters. 7.2. vref the cs4954/5 can operate with or without the aid of an external voltage reference. the cs4954/5 is designed with an internal voltage reference genera- tor that provides a vrefout signal at the vref pin. the internal voltage reference is utilized by not making a connection to the vref pin. the vref pin can also be connected to an external precision 1.232 volt reference, which then overrides the in- ternal reference. 7.3. iset all six of the cs4954/5 digital to analog converter dacs are output current normalized with a com- mon iset device pin. the dac output current per bit is determined by the size of the resistor connect- ed between iset and electrical ground. typically a 4k w , 1% metal film resistor should be used. the iset resistance can be changed by the user to ac- commodate varying video output attenuation via post filters and also to suit individual preferred per- formance. in conjunction with the iset value, the user can also independently vary the chroma, luma and col- orburst amplitude levels via host addressable con- trol register bits that are used to control internal digital amplifiers. the dac output levels are de- fined by the following operations: vref/riset = iref (e.g., 1.232 v/4k w = 308 m a ) cvbs/y/c/r/g/b outputs in low impedance mode: vout (max) = iref*(16/145)*1023*37.5 w = 1.304v cvbs/y/c/r/g/b outputs in high impedance mode: vout (max) = iref*(4/145)*1023*150 w =1.304v 7.4. dacs the cs4954/5 is equipped with six independent, video-grade, current-output, digital-to-analog con- verters (dacs). they are 10-bit dacs operating at a 27 mhz two-times-oversampling rate. all six dacs are disabled and default to a low power mode upon reset. each dac can be individually powered down and disabled. the output-current- per-bit of all six dacs is determined by the size of the resistor connected between the iset pin and electrical ground. 7.4.1. luminance dac the y pin is driven from a 10-bit 27 mhz current output dac that internally receives the y, or lumi- nance portion, of the video signal (black and white only). y is designed to drive proper video levels into a 37.5 w load. reference the detailed electrical section of this data sheet for the exact y digital to analog ac and dc performance data. a en_l en- able control bit in the control register 5 (005) is provided to enable or disable the luminance dac. for a complete disable and lower power operation the luminance dac can be totally shut down via the svidlum_pd control bit in the control regis- ter 4 (004). in this mode, turn-on through the con- trol register will not be instantaneous. 7.4.2. chrominance dac the c pin is driven from a 10-bit 27 mhz current output dac that internally receives the c or
cs4954 cs4955 ds278pp4 31 chrominance portion of the video signal (color only). c is designed to drive proper video levels into a 37.5 w load. reference the detailed electrical section of this data sheet for the exact c digital to analog ac and dc performance data. a en_c en- able control register bit in the control register 1 (005) is provided to enable or disable the chromi- nance dac. for a complete disable and lower power operation the chrominance dac can be to- tally shut down via the svidchr_pd register bit in the control register 4 (004). in this mode turn- on through the control register will not be instanta- neous. 7.4.3. cvbs dac the cvbs pin is driven from a 10-bit 27 mhz cur- rent output dac that internally receives a com- bined luma and chroma signal to provide composite video output. cvbs is designed to drive proper composite video levels into a 37.5 w load. reference the detailed electrical section of this data sheet for the exact cvbs digital to analog ac and dc performance data. the en_com enable con- trol register bit, in control register 1 (005), is provided to enable or disable the output pin. when disabled, there is no current flow from the output. for a complete disable and lower power operation, the cvbs37 dac can be totally shut down via the comdac_pd control register bit in control register 4 (004). in this mode turn-on through the control register will not be instantaneous. 7.4.4. red dac the red pin is driven from a 10-bit 27 mhz current output dac that internally receives a combined luma and chroma signal to provide composite vid- eo output. red is designed to drive proper compos- ite video levels into a 37.5 w load. reference the detailed electrical section of this data sheet for the exact red digital to analog ac and dc performance data. the en_r enable control register bit, in con- trol register 1 (005), is provided to enable or dis- able the output pin. when disabled, there is no current flow from the output. for a complete dis- able and lower power operation, the red dac can be totally shut down via the r_pd control register bit in control register 4 (004). in this mode turn- on through the control register will not be instanta- neous. 7.4.5. green dac the green pin is driven from a 10-bit 27 mhz cur- rent output dac that internally receives a com- bined luma and chroma signal to provide composite video output. green is designed to drive proper composite video levels into a 37.5 w load. reference the detailed electrical section of this data sheet for the exact green digital to analog ac and dc performance data. the en_g enable control register bit, in control register 1 (005), is provid- ed to enable or disable the output pin. when dis- abled, there is no current flow from the output. for a complete disable and lower power operation, the green dac can be totally shut down via the g_pd control register bit in control register 4 (004). in this mode turn-on through the control register will not be instantaneous. 7.4.6. blue dac the blue pin is driven from a 10-bit 27 mhz cur- rent output dac that internally receives a com- bined luma and chroma signal to provide composite video output. blue is designed to drive proper composite video levels into a 37.5 w load. reference the detailed electrical section of this data sheet for the exact blue digital to analog ac and dc performance data. the en_b enable control register bit, in control register 5 (005), is provid- ed to enable or disable the output pin. when dis- abled, there is no current flow from the output. for a complete disable and lower power operation, the blue dac can be totally shut down via the b_pd control register bit in control register 4 (004). in this mode turn-on through the control register will not be instantaneous.
cs4954 cs4955 32 ds278pp4 if some of the 6 dacs are not used, it is strongly recommended to power them down (see control_4 register) in order to reduce the pow- er dissipation. depending on the external resistor connected to the iset pin the output drive of the dacs can be changed. there are two modes in which the dacs should either be operated in. an external resistor of 4 k w must be connected to the iset pin. the first mode is the high impedance mode (low_imp bit set to 0). the dac outputs will then drive a double terminated load of 300 w and will output a video signal which conforms to the analog video specifications for ntsc and pal. external buffers will be needed if the dac output load differs from 300 w . the second mode is the low impedence mode (low_imp but set to 1). the dac output will then drive a double terminated load of 75 w and will output a video signal which conforms to the analog video specifications for ntsc and pal. no external buffers are necessary, the ouputs can di- rectly drive a television input. note that for power dissipation purposes it is not always possible to have all the 6 dacs active at the same time. table 8 shows the maximum allowed active dacs depending on the power supply and low/high impedance modes. if less than 6 dacs are allowed to be active the other ones must be power down (see control_4 register). 8. programming 8.1. host control interface the cs4954/5 host control interface can be config- ured for i 2 c or 8-bit parallel operation. the cs4954/5 will default to i 2 c operation when the rd and wr pins are both tied low at power up. the rd and wr pins are active for 8-bit parallel oper- ation only. 8.1.1. i 2 c interface the cs4954/5 provides an i 2 c interface for access- ing the internal control and status registers. exter- nal pins are a bidirectional data pin (sda) and a serial input clock (scl). the protocol follows the i 2 c specifications. a complete data transfer is shown in figure 26. note that this i 2 c interface will work in slave mode only - it is not a bus master. sda and scl are connected via an external pull- up resistor to a positive supply voltage. when the bus is free, both lines are high. the output stages of devices connected to the bus must have an open- drain or open-collector in order to perform the wired-and function. data on the i 2 c bus can be nominal power supply low/high impedance mode maximum # of active dacs 3.3v low impedance 3 3.3v high impedance 6 5.0v low impedance 3 5.0v high impedance 6 table 8. maximum dac numbers sda scl a p start address 1-7 r/w 8 9 ack 1-7 data 89 1-7 8 9 ack data ack stop note: i 2 c transfers data always with msb first, lsb last figure 26. i 2 c protocol
cs4954 cs4955 ds278pp4 33 transferred at a rate of up to 400 kbits/sec in fast mode. the number of interfaces to the bus is solely dependent on the limiting bus capacitance of 400 pf. when 8-bit parallel interface operation is being used, sda and scl can be tied directly to ground. the i 2 c bus address for the cs4954/5 is program- mable via the i2c_adr register (0 0f). when i 2 c interface operation is being used, rd and wr must be tied to ground. pdat [7:0] are available to be used for gpio operation in i 2 c host interface mode. for 3.3 v operation it is necessary to have the appropriate level shifting for i 2 c signals. 8.1.2. 8-bit parallel interface the cs4954/5 is equipped with a full 8-bit parallel microprocessor write and read control port. along with the pdat [7:0] pins, the control port interface is comprised of host read (rd ) and host write (wr ) active low strobes and host address enable (addr), which, when low, enables unique address register accesses. the control port is used to access internal registers which configure the cs4954/5 for various modes of operation. the internal registers are uniquely addressed via an address register. the address register is accessed during a host write cy- cle with the wr and addr pins set low. host write cycles with addr set high will write the 8- bits on the pdat [7:0] pins into the register cur- rently selected by the address register. likewise read cycles occur with rd set low and addr set high will return the register contents selected by the address register. reference the detailed electrical timing parameter section of this data sheet for exact host parallel interface timing characteristics and specifications. t rec t rec wr rd figure 27. 8-bit parallel host port timing: read-write/write-read cycle addr rd pdat[7:0] t rd t rpw t rah t rda t rdh t as figure 28. 8-bit parallel host port timing: address read cycle
cs4954 cs4955 34 ds278pp4 8.2. register description a set of internal registers are available for control- ling the operation of the cs4954/5. the registers extend from internal address 0 00 through 05a. table 9 shows a complete list of these registers and their internal addresses. note that this table and the subsequent register description section describe the full register map for the cs4954 only. a complete cs4955 register set description is available only to macrovision acp-ppv licensed buyers. 8.2.1. control registers wr addr pdat[7:0] t as t wds t wdh t wpw t wr t wac figure 29. 8-bit parallel host port timing: address write cycle address register name type default value 0 00 control_0 r/w 01h 0 01 control_1 r/w 02h 0 02 control_2 r/w 00h 0 03 control_3 r/w 00h 0 04 control_4 r/w 3fh 0 05 control_5 r/w 00h 0 06 control_6 r/w 00h 0 07 reserved 0 08 bkg_color r/w 03h 0 09 gpio_ctrl_reg r/w 00h 0 0a gpio_data_reg r/w 00h 0 0b reserved 0 0c reserved 0 0d sync_0 r/w 90h 0 0e sync_1 r/w f4h 0 0f i 2 c_adr r/w 00h 0 10 sc_amp r/w 1ch 0 11 sc_synth0 r/w 3eh 0 12 sc_synth1 r/w f8h 0 13 sc_synth2 r/w e0h 0 14 sc_synth3 r/w 43h 0 15 hue_lsb r/w 00h 0 16 hue_msb r/w 00h table 9. control registers
cs4954 cs4955 ds278pp4 35 0 17 sch phase adjust r/w 00h 0 18 cc_en r/w 00h 0 19 cc_21_1 r/w 00h 0 1a cc_21_2 r/w 00h 0 1b cc_284_1 r/w 00h 0 1c cc_284_2 r/w 00h 0 1d reserved 0 1e wss_reg_0 r/w 00h 0 1f wss_reg_1 r/w 00h 0 20 wss_reg_2 r/w 00h 0 21 reserved 0 22 cb_amp r/w 80h 0 23 cr_amp r/w 80h 0 24 y_amp r/w 80h 0 25 r_amp r/w 80h 0 26 g_amp r/w 80h 0 27 b_amp r/w 80h 0 28 bright_offset r/w 00h 0 29 ttxhs r/w a1h 0 2a ttxhd r/w 02h 0 2b ttxovs r/w 00h 0 2c ttxove r/w 00h 0 2d ttxevs r/w 00h 0 2e ttxeve r/w 00h 0 2f ttx_dis1 r/w 00h 0 30 ttx_dis2 r/w 00h 0 31 ttx_dis_3 r/w 00h 0 32 int_en r/w 00h 0 33 int_clr r/w 00h 0 34 status_0 read only 0 35 - 0 59 reserved 0 5a status_1 read only 04h 0 61 - 0 7f reserved address register name type default value table 9. control registers (continued)
cs4954 cs4955 36 ds278pp4 control register 0 address 0 00 control_0 read/write default value = 01h control register 1 address 0 01 control_1 read/write default value = 02h bit number 76543210 bit name tv_fmt mstr ccir656 prog in_mode cbcr_uv default 00000001 bit mnemonic function 7:5 tv_fmt selects the tv display format 000: ntsc-m ccir601 timing (default) 001: ntsc-m rs170a timing 010: pal-b, d, g, h, i 011: pal-m 100: pal-n (argentina) 101: pal-n (non argentina) 110-111: reserved 4mstr 1 = master mode, 0 = slave mode 3 ccir656 video input is in itu r.bt656 format (0 = off, 1 = on) 2prog progressive scanning enable (enable = 1) 1 in_mode input select (0 = solid background, 1 = use v [7:0] data) 0 cbcr_uv enable ycbcr to yuv conversion (1 = enable, 0 = disable) bit number 76543210 bit name lum del ch bw lpf_on rgb_bw fld ped cbcrsel default 00000010 bit mnemonic function 7:6 lum del luma delay on the composite1 output 00: no delay (default) 01: 1 pixel clock delay 10: 2 pixel clock delay 11: 3 pixel clock delay 5 ch bw chroma lpf bandwidth (0 = 650 khz, 1 = 1.3 mhz) 4lpf on chroma lpf on/off (0 = off, 1 = on) 3rgb_bw 0 = full bandwidth on rgb, 1 = bw reduced to 2.5 mhz (3 db point) (default 0) 2fld_pol polarity of field (0: odd field = 0,1: odd field = 1) 1 ped pedestal offset (0: 0 ire, 1: 7.5 ire) 0 cbcrsel cbcr select (0 = chroma undelayed, 1 = chroma delayed by one clock)
cs4954 cs4955 ds278pp4 37 control register 2 address 0 02 control_2 read/write default value = 00h bit number 76543210 bit name output format ttx wst ttx en sync_dly xtal sc_en default 00000000 bit mnemonic function 7:5 output format selects the output through the dacs 000 : rgb, s-video, composite1 (6 dacs) (default) 001 : yuv, s-video, composite1 (6 dacs) 010 : s-video, composite1, composite2, (4 dacs) 011 : rgb, composite1, composite2 (5 dacs) 100 : yuv, composite1, composite2 (5 dacs) 101-111: dont care 4 ttx wst to select between world standard (ntsc), world standard (pal), or north american teletext standard during ntsc or pal modes (1 = wst ttx) (default is 0) in ntsc-m or pal-m mode. this bit works in conjunction with the tv format register. 0: nabts, if tv format is ntsc or pal-m 1: wst (ntsc), if tv format is ntsc or pal-m 0: europe ttx, if tv format is pal-b, g..., n 1: wst (pal), if tv format is pal-b, g, ..., n 3 ttx en enable teletext process (1 = enable) 2 sync dly slave mode 1 pixel sync delay (1 = enable) 1xtal crystal oscillator for subcarrier adjustment enable (1 = enable) 0bu dis chroma burst disable (1 = disable)
cs4954 cs4955 38 ds278pp4 control register 3 address 0 03 control_3 read/write default value = 00h control register 4 address 0 04 control_4 read/write default value = 3fh bit number 76543210 bit name reserved fd thr c1 fd thr c2 fd thr sv fd thr en cbar default 00000000 bit mnemonic function 7:5 - reserved 4fd thr c1 feedthrough enabled for composite 1 output (0 = off, 1 = on) 3fd thr c2 feedthrough enabled for composite 2 output (0 = off, 1 = on) 2fd thr sv feedthrough enabled for s-video (on luma signal) (0 = off, 1 = on) 1fd thr_en enable (1 = enable) input to feed through during inactive lines 0 cbar internal color bar generator (0 = off, 1 = on) bit number 76543210 bit name cb_h_sel cb_fld_sel comdac_pd svidlum_pd svidchr_pd r_pd g_pd b_pd default 00111111 bit mnemonic function 7 cb_h_sel composite blank / hsync output select (1 = cb select, 0 = hsync select) 6 cb_fld_sel composite blank / field output select (1 = cb select, 0 = hsync select) 5 comdac_pd power down composite dac 0: power up, 1: power down 4 svidlum_pd power down luma s-video dac 0: power up, 1: power down 3 svidchr_pd power down chroma s-video dac 0: power up, 1: power down 2r_pd power down red rgb video dac 0: power up, 1: power down 1g_pd power down green rgb video dac 0: power up, 1: power down 0b_pd power down blue rgb video dac 0: power up, 1: power down
cs4954 cs4955 ds278pp4 39 control register 5 address 0 05 control_5 read/write default value = 00h control register 6 address 0 06 control_6 read/write default value = 00h bit number 76543210 bit name rsvd low imp en com en len cen ren gen b default 00000000 bit mnemonic function 7- reserved 6low imp selects between high output impedance (0) or low output impedance (1) mode of dacs 5en com enable dac for composite output 0: tri-state, 1: enable 4en l enable s-video dac for luma output 0: tri-state, 1: enable 3en c enable s-video dac for chroma output 0: tri-state, 1: enable 2en_r enable rgb video dac for red output 0: tri-state, 1: enable 1en_g enable rgb video dac for green output 0: tri-state, 1: enable 0en_b enable rgb video dac for blue output 0: tri-state, 1: enable bit number 76543210 bit name 656 sync out clip off ttxen com2 ttxen com1 ttxen svid bsync dis gsync dis rsync dis default 00000000 bit mnemonic function 7 656 sync out enable (=1) output of hsync and vsync in the itu r.bt656 mode 6clip off clipping input signals disable (0: clipping active 1: no clipping) 5 ttxen com2 enable teletext at the composit2 output (0: disable teletext, 1 : enable teletext) 4 ttxen com1 enable teletext at the composit1 output ( 0: disable teletext, 1 : enable teletext) 3 ttxen svid enable teletext at the s-video output ( 0: disable teletext, 1: enable teletext) 2 bsync dis disable syncs in the blue or v output (0: enable syncs, 1: disable syncs) 1 gsync dis disable syncs in the green or u output ( 0: enable syncs, 1: disable syncs) 0 rsync dis disable syncs in the red or y output (0: enable syncs, 1: disable syncs)
cs4954 cs4955 40 ds278pp4 background color register address 0 08 bkg_color read/write default value = 03h gpio control register address 0 09 gpio__reg read/write default value = 00h gpio data register address 0 0a gpio_reg read/write default value = 00h sync register 0 address 0 0d sync_0 read/write default value = 90h bit number 76543210 bit name bg default 00000011 bit mnemonic function 7:0 bg background color (7:5 = r, 4:2 = g, 1:0 = b) (default is 0000 0011 - blue) bit number 76543210 bit name gpr_cntrl default 00000000 bit mnemonic function 7:0 gpr cntrl input(0)/output(1) control of gpio registers (bit 0: pdat(0), bit 7: pdat(7)) bit number 76543210 bit name gpio reg default 00000000 bit mnemonic function 7:0 gpio reg gpio data register ( data is output on pdat bus if appropriate bit in address 09 is set to 1, otherwise data is input/output through i 2 c)- this register is only accessible in i 2 c mode. bit number 76543210 bit name prog vs[4:0] prog hs[10:8] default 10010000 bit mnemonic function 7:3 prog vs[4:0] programmable vsync lines 2:0 prog hs[10:8] programmable hsync pixels (3 most significant bits)
cs4954 cs4955 ds278pp4 41 sync register 1 address 0 0e sync_1 read/write default value = f4h i 2 c address register address 0 0f i 2 c_adr read/write default value = 00h subcarrier amplitude register address 0 10 sc_amp read/write default value = 1ch subcarrier synthesis register address 0 11 sc_synth0 read/write default value = 3eh 0 12 sc_synth1 f8h 0 13 sc_synth2 e0h 0 14 sc_synth3 43h bit number 76543210 bit name prog hs[7:0] default 11110100 bit mnemonic function 7:0 prog hs[7:0] programmable hsync pixels lsb bit number 76543210 bit name reserved i 2 c adr default 00000000 bit mnemonic function 7- reserved 6:0 i 2 c i 2 c device address (programmable) bit number 76543210 bit name bu amp default 00011100 bit mnemonic function 7:0 bu amp color burst amplitude register bits mnemonic function sc_synth0 7:0 cc 0 subcarrier synthesis bits 7:0 sc_synth1 7:0 cc 1 subcarrier synthesis bits 15:8 sc_synth2 7:0 cc 2 subcarrier synthesis bits 23:16 sc_synth3 7:0 cc 3 subcarrier synthesis bits 31:24
cs4954 cs4955 42 ds278pp4 hue lsb adjust register address 0 15 hue_lsb read/write default value = 00h hue msb adjust register address 0 16 hue_msb read/write default value = 00h sch sync phase adjust address 0 17 sch read/write default value = 00h closed caption enable register address 0 18 cc_en read/write default value = 00h bit number 76543210 bit name hue lsb default 00000000 bit mnemonic function 7:0 hue lsb 8 lsbs for hue phase shift bit number 76543210 bit name reserved msb default 00000000 bit mnemonic function 7:2 - reserved 1:0 hue msb 2 msbs for hue phase shift bit mnemonic function 7:0 sch default - 00h in increments of ? 1.4 degree per bit up to 360 bit number 765432 1 0 bit name reserved en_284 en_21 default 000000 0 0 bit mnemonic function 7:2 - reserved 1 cc en[1] enable closed caption for line 284 0 cc en[0] enable closed caption for line 21
cs4954 cs4955 ds278pp4 43 closed caption data register address 0 19 cc_21_1 read/write default value = 00h 0 1a cc_21_2 00h 0 1b cc_284_1 00h 0 1c cc_284_2 00h wide screen signaling register 0 address 0 1e wss_reg_0 read/write default value = 00h bit mnemonic function 7:0 cc_21_1 first closed caption databyte of line 21 7:0 cc_21_2 second closed caption databyte of line 21 7:0 cc_284_1 first closed caption databyte of line 284 7:0 cc_284_2 second closed caption databyte of line 284 bit number 765432 1 0 bit name wss_23 wss_22 wss_21 wss_20 wss_19 wss_18 wss_17 wss_16 default 000000 0 0 bit mnemonic function 7 wss_23 enable wide screen signalling (enable =1) 6 wss_22 pal: enable wss (enable = 1) on line 23 of field 2, ntsc: dont care 5 wss_21 pal: group 4, bit 13, ntsc: dont care 4 wss_20 pal: group 4, bit 12, ntsc: dont care 3 wss_19 pal: group 4, bit 11, ntsc: bit 20 2 wss_18 pal: group 3, bit 10, ntsc: bit 19 1 wss_17 pal: group 3, bit 9, ntsc: bit 18 0 wss_16 pal: group 3, bit 8, ntsc: bit 17
cs4954 cs4955 44 ds278pp4 w ide screen signalling register 1 address 0 1f wss_reg_1 read/write default value = 00h wide screen signalling register 2 address 0 20 wss_reg_2 read/write default value = 00h f ilter register 0 address 0 22 cb_amp read/write default value = 80h bit number 765432 1 0 bit name wss_15 wss_14 wss_13 wss_12 wss_11 wss_10 wss_9 wss_8 default 000000 0 0 bit mnemonic function 7 wss_15 pal: group 2, bit 7, ntsc: bit 16 6 wss_14 pal: group 2, bit 6, ntsc: bit 15 5 wss_13 pal: group 2, bit 5, ntsc: bit 14 4 wss_12 pal: group 2, bit 4, ntsc: bit 13 3 wss_11 pal: group 1, bit 3, ntsc: bit 12 2 wss_10 pal: group 1, bit 2, ntsc: bit 11 1 wss_9 pal: group 1, bit 1, ntsc: bit 10 0 wss_8 pal: group 1, bit 0, ntsc: bit 9 bit number 765432 1 0 bit name wss_7 wss_6 wss_5 wss_4 wss_3 wss_2 wss_1 wss_0 default 000000 0 0 bit mnemonic function 7 wss_7 pal: dont care, ntsc: bit 8 6 wss_6 pal: dont care, ntsc: bit 7 5 wss_5 pal: dont care, ntsc: bit 6 4 wss_4 pal: dont care, ntsc: bit 5 3 wss_3 pal: dont care, ntsc: bit 4 2 wss_2 pal: dont care, ntsc: bit 3 1 wss_1 pal: dont care, ntsc: bit 2 0 wss_0 pal: dont care, ntsc: bit 1 bit number 76543210 bit name u_amp default 10000000 bit mnemonic function 7:0 u_amp u(cb) amplitude coefficient
cs4954 cs4955 ds278pp4 45 f ilter register 1 address 0 23 cr_amp read/write default value = 80h f ilter register 2 address 0 24 y_amp read/write default value = 80h f ilter register 3 address 0 25 r_amp read/write default value = 80h f ilter register 4 address 0 26 g_amp read/write default value = 80h bit number 76543210 bit name v_amp default 10000000 bit mnemonic function 7:0 v_amp v(cr) amplitude coefficient bit number 76543210 bit name y_amp default 10000000 bit mnemonic function 7:0 y_amp luma amplitude coefficient bit number 76543210 bit name r_amp default 10000000 bit mnemonic function 7:0 r_amp red amplitude coefficient bit number 76543210 bit name g_amp default 10000000 bit mnemonic function 7:0 g_amp green amplitude coefficient
cs4954 cs4955 46 ds278pp4 f ilter register 5 address 0 27 b_amp read/write default value = 80h f ilter register 6 address 0 28 bright_offsett read/write default value = 00h teletext register 0 address 0 29 ttxhs read/write default value = a1h t eletext register 1 address 0 2a ttxhd read/write default value = 02h bit number 76543210 bit name b_amp default 10000000 bit mnemonic function 7:0 b_amp blue amplitude coefficient bit number 76543210 bit name brightness_offset default 00000000 bit mnemonic function 7:0 brght_offset brightness adjustment ( range: -128 to +127) bit number 76543210 bit name ttxhs default 10100001 bit mnemonic function 7:0 ttxhs start of teletext request pulses or start of window bit number 76543210 bit name ttxhd default 00000010 bit mnemonic function 7:0 ttxhd if ttx_window = 0 then this register is used as the pipeline delay between ttxrq and ttxdat signal in the teletext source. user programmable delay step of 37 ns per lsb. if ttx_window = 1 then this register is used as the 8 lsbs of the teletext insertion windows; the 3 msbs are located in register 031. (register 031 bit 3)
cs4954 cs4955 ds278pp4 47 teletext register 2 address 0 2b ttxovs read/write default value = 00h t eletext register 3 address 0 2c ttxove read/write default value = 00h teletext register 4 address 0 2d ttxevs read/write default value = 00h t eletext register 5 address 0 2e ttxeve read/write default value = 00h bit number 76543210 bit name ttxovs default 00000000 bit mnemonic function 7:0 ttxovs start of teletext line window in odd field bit number 76543210 bit name ttxove default 00000000 bit mnemonic function 7:0 ttxove end of teletext line window in odd field bit number 76543210 bit name ttxevs default 00000000 bit mnemonic function 7:0 ttxevs start of teletext line window in even field bit number 76543210 bit name ttxeve default 00000000 bit mnemonic function 7:0 ttxeve end of teletext line window in even field
cs4954 cs4955 48 ds278pp4 teletext register 6 address 0 2f ttx_dis1 read/write default value = 00h t eletext register 7 address 0 30 ttx_dis2 read/write default value = 00h t eletext register 8 address 0 31 ttx_dis3 read/write default value = 00h bit number 76543210 bit name ttx_line_dis1 default 00000000 bit mnemonic function 7:0 ttx_line_dis1 teletext disable bits corresponding to the lines 5-12 respectively, (11111111=all eight lines are disabled), (msb is for line 5, lsb is for line 12) bit number 76543210 bit name ttx_line_dis2 default 00000000 bit mnemonic function 7:0 ttx_line_dis2 teletext disable bits corresponding to the lines 13-20 respectively, (11111111=all eight lines are disablled, (msb is for line 13, lsb is for line 20) bit number 765 4 3 210 bit name ttxhd reserved ttx_window ttx_line_dis3 default 000 0 0 000 bit mnemonic function 7:5 ttxhd if ttx_window = 0 these 3 bits are unused. if ttx_window = 1 these 3 bits are the msbs of the register 02a; they are used to specify the length of the teletext insertion window 4 reserved 3 ttx_window selects between ttxrq (= 0) pulsation or ttxrq (= 1) window mode 2:0 ttx_line_dis3 teletext disable bits corresponding to the lines 13-20 respectively, (111=all three lines are disabled), (msb is for line 21, lsb is for line 23)
cs4954 cs4955 ds278pp4 49 interrupt register 0 address 0 32 int_en read/write default value = 00h interrupt register 1 address 0 33 int_clr read/write default value = 00h status register 0 address 0 34 status_0 read only default value = 00h status register 1 address 0 5a status_1 read only default value = 04h bit number 76543 2 1 0 bit name reserved int_21_en int_284_en int_v_en default 00000 0 0 0 bit mnemonic function 7:3 - reserved 2 int_21_en interrupt enable for closed caption line 21 1 int_284_en interrupt enable for closed caption line 284 0int_v_en interrupt enable for new video field bit number 76543 2 1 0 bit name reserved clr_int_21 clr_int_284 clr_int_v default 00000 0 0 0 bit mnemonic function 7:3 - reserved 2 clr_int_21 clear interrupt for closed caption line 21 (int 21) 1 clr_int_284 clear interrupt for closed caption line 284 (int_284) 0 clr_int_v clear interrupt for new video field (int_v) bit number 543 2:0 bit name int_21 int_284 int_v fld default 000 0 bit mnemonic function 5int_21 interrupt flag for line 21 (closed caption) complete 4 int_284 interrupt flag for line 284 (closed caption) complete 3int_v interrupt flag for video field change 2:0 fld_st field status bits(001 = field 1,000 = field 8) bit number 76543210 bit name device_id default 00000100 bit mnemonic function 7:0 device_id device identification: cs4954: 0000 0100, cs4955: 0000 0101
cs4954 cs4955 50 ds278pp4 9. board design and layout considerations the printed circuit layout should be optimized for lowest noise on the cs4954/5 placed as close to the output connectors as possible. all analog supply traces should be as short as possible to minimize in- ductive ringing. a well designed power distribution network is es- sential in eliminating digital switching noise. the ground planes must provide a low-impedance re- turn path for the digital circuits. a pc board with a minimun of four layers is recommended. the ground layer should be used as a shield to isolate noise from the analog traces. the top layer (1) should be reserved for analog traces but digital traces can share this layer if the digital signals have low edge rates and switch little current or if they are separated from the analog traces by a signigicant distance (dependent on their frequency content and current). the second layer should then be the ground plane followed by the analog power plane on layer three and the digital signal layer on layer four. 9.1. power and ground planes the power and ground planes need isolation gaps of at least 0.05 " to minimize digital switching noise effects on the analog signals and components. a split analog/digital ground plane should be con- nected at one point as close as possible to the cs4954/5. 9.2. power supply decoupling start by reducing power supply ripple and wiring harness inductance by placing a large (33-100 uf) capacitor as close to the power entry point as pos- sible. use separate power planes or traces for the digital and analog sections even if they use the same supply. if necessary, further isolate the digital and analog power supplies by using ferrite beads on each supply branch followed by a low esr capac- itor. place all decoupling caps as close as possible the the device as possible. surface mount capacitors generally have lower inductance than radial lead or axial lead components. surface mount caps should be place on the component side of the pcb to min- imize inductance caused by board vias. any vias, especially to ground, should be as large as possible to reduce their inductive effects. 9.3. digital interconnect the digital inputs and outputs of the cs4954/5 should be isolated from the analog outputs as much as possible. use separate signal layers whenever possible and do not route digital signals over the analog power and ground planes. noise from the digital section is related to the digi- tal edge rates used. ringing, overshoot, under- shoot, and ground bounce are all related to edge rate. use lower speed logic such as hcmos for the host port interface to reduce switching noise. for the video input ports, higher speed logic is re- quired, but use the slowest practical edge rate to re- duce noise. to reduce noise, it is important to match the source impedance, line impedance, and load impedance as much as possible. generally, if the line length is greater than one fourth the signal edge rate, line termination is necessary. ringing can also be reduced by damping the line with a se- ries resistor (22-150 w ). under extreme cases, it may be advisable to use microstrip techniques to further reduce radiated switching noise if very fast edge rates (<2ns) are used. if microstrip techniques are used, split the analog and digital ground planes and use proper rf decoupling techniques. 9.4. analog interconnect the cs4954/5 should be located as close as possi- ble the output connectors to minimize noise pickup and reflections due to impedance mismatch. all un- used analog outputs should be placed in shutdown. this reduces the total power that the cs4954/5 re- quires, and eliminates the impedance mismatch
cs4954 cs4955 ds278pp4 51 presented by an unused connector. the analog out- puts should not overlay the analog power plane to maximize high frequency power supply rejection. 9.5. analog output protection to minimize the possibility of damage to the ana- log output sections, make sure that all video con- nectors are well grounded. the connector should have a good dc ground path to the analog and dig- ital power supply grounds. if no dc (and low fre- quency) path is present, improperly grounded equipment can impose damaging reverse currents on the video out lines. therefore, it is also a good idea to use output filters that are ac coupled to avoid any problems. 9.6. esd protection all mos devices are sensitive to electro static discharge (esd). when manipulating these devic- es, proper esd precautions are recommended to avoid performance degradation or permanent dra- mage. 9.7. external dac output filter if an output filter is required, the low pass filter shown in figure 30 can be used. 2.2 m h 330pf 220pf out in c 1 c 2 figure 30. external low pass filter c 2 should be chosen so that c 1 = c 2 + c cable
cs4954 cs4955 52 ds278pp4 figure 31. typical connection diagram ferrite bead l1 vcc 17 36 41 38 39 40 43 44 48 47 12 34 37 18 34 42 45 15 14 16 30 31 26-19 27 28 32 33 29 8 8-1 9 10 11 13 xtalin xtalout paddr ttxdat ttxrq pdat[7:0] rd wr sda scl clk v[7:0] field hsync vsync gnda y c cvbs red green blue int reset i 2 c controller vcc vaa vref composite video connector 75 or 300 w 75 or 300 w s-video connector 75 or 300 w 4k w 1% /cb test 27 mhz clock pixel data 110 w 110 w 1.5 k w 1.5 k w gpio port nc 4.7 m f 0.1 m f 300 w 300 w 300 w cs4954 cs4955 75 or 75 or 75 or /cb to scart connector iset 46 gndd vdd
cs4954 cs4955 ds278pp4 53 10. pin description b cvbs gnda vaa c y v0 v1 v2 v3 v4 v5 v6 v7 field /cb hsync /cb vsync int test xtal_out xtal_in padr vdd gndd gnda vaa g r vref iset vaa gnda reset scl sda ttxrq ttxdat clkin wr rd pdat0 pdat1 pdat2 pdat3 pdat4 pdat5 pdat6 pdat7 cs4954-cq CS4955-CQ 48-pin tqfp top view 48 47 46 45 44 43 41 42 40 39 38 37 13 14 15 16 17 18 20 19 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12
cs4954 cs4955 54 ds278pp4 pin name pin number type description v [7:0] 8, 7, 6, 5, 4, 3, 2, 1 in digital video data inputs clk 29 in 27 mhz input clock paddr 16 in address enable line xtal_in 15 in subcarrier crystal input xtal_out 14 out subcarrier crystal output hsync /cb 10 i/o active low horizontal sync, or composite blank signal vsync 11 i/o active low vertical sync. field/cb 9 out video field id. selectable polarity or composite blank rd 27 in host parallel port read strobe, active low wr 28 in host parallel port write strobe, active low pdat [7:0] 19, 20, 21, 22, 23, 24, 25, 26 i/o host parallel port/ general purpose i/o sda 32 i/o i 2 c data scl 33 in i 2 c clock input cvbs 44 current composite video output y 48 current luminance analog output c 47 current chrominance analog output r 39 current red analog output g 40 current green analog output b 43 current blue analog output vref 38 i/o internal voltage reference output or external refer- ence input iset 37 current dac current set ttxdat 30 in teletext data input ttxrq 31 out teletext request output int 12 out interrupt output, active high reset 34 in active low master reset test 13 in test pin. ground for normal operation vaa 36, 41, 46 ps + 5 v or + 3.3 v supply (must be same as vdd) gndd 18 ps ground vdd 17 ps +5 v or 3.3 v supply (must be same as vaa) gnda 35, 42, 45 ps ground table 10. device pin description s
cs4954 cs4955 ds278pp4 55 11. package drawing inches millimeters dim min max min max a --- 0.063 --- 1.60 a1 0.002 0.006 0.05 0.15 b 0.007 0.011 0.17 0.27 d 0.343 0.366 8.70 9.30 d1 0.272 0.280 6.90 7.10 e 0.343 0.366 8.70 9.30 e1 0.272 0.280 6.90 7.10 e* 0.016 0.024 0.40 0.60 l 0.018 0.030 0.45 0.75 0.000 7.000 0.00 7.00 * nominal pin pitch is 0.50 mm controlling dimension is mm. jedec designation: ms026 48l tqfp package drawing e1 e d1 d 1 e l b a1 a

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